[libre-riscv-dev] next tasks

Luke Kenneth Casson Leighton lkcl at lkcl.net
Wed Feb 19 14:14:16 GMT 2020

we only have a few months in which to hang together all of the pieces
that have been put together, to make a 64-bit 180nm chip.  because
we're not doing this in verilog i believe it is reasonably doable, if
we take steps to cut "unnecessary" things out i.e. not do too much.
chop out L2 cache for example.

two obviously important tasks:

1) a POWER ISA decoder and CSR infrastructure
2) a RISC-V ISA decoder and CSR infrastructure

samuel has the new kcp5 stuff, you made a good start on (2) - i'd like
to borrow that if that's ok :)  and if you['re still around, have
time, and wanted to complete it to the point where it's useable for
our project, that would be handy.

michael would you like to have a go at writing a POWER ISA decoder?


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