[libre-riscv-dev] Vulkanizing

Veera vklr at vkten.in
Wed Feb 19 07:07:35 GMT 2020

On Wed, Feb 19, 2020 at 06:40:38AM +0000, Immanuel, Yehowshua U wrote:
> > it's slready extremely clear and simple.  so simple that you're not getting
> > it.
> That’s my favorite kind of simple.
> Yehowshua

Actually, RISC-V had opcode space for many functions. And initially
IMAFD was only developed when initially released. If you read up
about RISC-V, they had planned for SIMD, Vector, Bit Manipulation,
Decimal FP, etc.

If I am right, the need to switch to OPENPOWER ISA had begun
because they declined to include opcode space Luke wanted in and
also to be recognized as RISC-V part.

I think RISC-V Foundation want their way of doing things. Since
they started from zero when developing RISC-V architecture using
only the information about CPU designing and architectures
developed till then. And they explicitly say they leave enough
of opcode space for custom things by others.

I do not exact reasons Luke had. And I have not read RISC-V
mailing list also for a time.


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