[libre-riscv-dev] Vulkanizing

Immanuel, Yehowshua U yimmanuel3 at gatech.edu
Wed Feb 19 06:42:07 GMT 2020

> The current plan is to have the main (mul-add) SIMD ALU be 128-bits wide
> per-core. That is 8 flops/core/cycle of fp32, 16 for fp16, and, depending
> on how we implement it, either 2 or 4 flops/core/cycle of fp64. There are
> also other ALUs for div (int and fp), sqrt, rsqrt, and other special
> functions, so those will help increase performance too.

Yes this make sense.

OK, I’ve got a rough idea of what we’re doing now.
We have 4 CPU cores right?

So that’s 4 128-bit wide ALU.
Gosh, that’s a lot of gates, and dynamic partitioning - cool - but a little tricky…

But sounds good nonetheless.


More information about the libre-riscv-dev mailing list