[libre-riscv-dev] Vulkanizing

Jacob Lifshay programmerjake at gmail.com
Wed Feb 19 06:31:49 GMT 2020

On Tue, Feb 18, 2020, 22:10 Immanuel, Yehowshua U <yimmanuel3 at gatech.edu>

> I guess I should say, how many SIMD lanes do we have…

The current plan is to have the main (mul-add) SIMD ALU be 128-bits wide
per-core. That is 8 flops/core/cycle of fp32, 16 for fp16, and, depending
on how we implement it, either 2 or 4 flops/core/cycle of fp64. There are
also other ALUs for div (int and fp), sqrt, rsqrt, and other special
functions, so those will help increase performance too.

> And guys, to be honest, I have a good feeling about this.
> Our design should be SUPER easy to scale to something like a server scale
> processors. Provided we solve the interconnect problem that accompanies
> scaling…

We've been thinking about using OmniXpress (basically TileLink wrapped in
ethernet) as a chip-to-chip memory-coherent interconnect because we can
share the ethernet port i/o pins between both of them and use off-the-shelf
ethernet switches. Also, since it sent using bog-standard ethernet, we can
use the i/o pins for both interconnect and tcp/ip at the same time.

see http://bugs.libre-riscv.org/show_bug.cgi?id=70


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