[libre-riscv-dev] [Bug 168] create naturally aligned partition points

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=168

--- Comment #2 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
ok so the idea is, that the only options for partition sizes are:

* 64
* 32,32
* 16,16,16,16
* 8,8,8,8,8,8,8,8

is that the idea?

if so, this restricts us to not being able to run 32-bit arithmetic in one
"lane" and 16-16 bit arithmetic in the other.

the way that the 6600 engine and register file is to be arranged is that
the register file is subdivided 32-HI, 32-LO times two.  so, four ports,
but only 32-bit-wide.  if you want to do 64-bit arithmetic, you have to
use *two* of those ports.

also, each *byte* of the register file has its own write-enable line.

this so that on vectorised instructions, if there are 32-bit instructions
that happen to hit the 32-LO register port, the 32-*HI* port can be used
for 32, 16-16, 8-8-8-8 *completely different* instructions that *HAPPEN*
to occur (or are deliberately arranged to occur) on the exact same cycle
and happen to be the exact same operation.

now, whether these conditions turn out to be reasonable or not is another
matter, hence why, yeah, it should be fine to consider this, and thus
perhaps greatly simplify the partitioning.

would we end up with a huge number of 32-bit-adds mixed in with 8-8-8-8
adds?  i don't honestly know.

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