[libre-riscv-dev] Routing a first nmigen disign with Corilis

[Luke Kenneth Casson Leighton]

On Mon, Feb 10, 2020 at 9:30 PM Jean-Paul Chaput
<Jean-Paul.Chaput at lip6.fr> wrote:

> > hmm... last thing: opens arm_chips_cts_r_ext.vst (attached).
>
>   That's strange that I do not have the same problem at my end.

ah i am running "make -j16" and i *think* there may be missing
dependencies in Makefiles, causing not just files to be done out of
order (usually at the linker phase) but also potentially running
commands *twice*.

this would explain the overwriting, if a file is being opened (and
written to) twice, simultaneously.

recompiled alliance with CFLAGS="-g3 -O0"

(gdb) print losig_pnt
$1 = (struct losig *) 0x557732e0
(gdb) print *losig_pnt
Cannot access memory at address 0x557732e0
(gdb) print losig_pnt->NEXT
Cannot access memory at address 0x557732e0

>   Even if lvx has failed you can use "make cgt" to at least see
>   the layout (try the print function to have a nice picture ;-) )

ooooo preeettyyyyy ;)

> > i know "what" to expect, from a high level, if you know what i mean.
> > plus i've done PCB layout.  and gate-level design.  and electronics
> > circuits.  and, and, and...
>
>   No offense intended!

none intended here either.

> In ASICs, Le Diable est dans les détails!

true :)

> > niiice!  that's going in the notes...
>
>   Argh! This is still the "old" (like, one week old) version of the doc which is
>   generated by sphinx.

ok yes the git checkout was indeed from a week ago.

l.
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