[libre-riscv-dev] Routing a first nmigen disign with Corilis

Jean-Paul Chaput Jean-Paul.Chaput at lip6.fr
Mon Feb 10 21:35:15 GMT 2020


On Mon, 2020-02-10 at 21:11 +0000, Luke Kenneth Casson Leighton wrote:
> ---
> crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68
> 
> On Mon, Feb 10, 2020 at 8:30 PM Jean-Paul Chaput
> <Jean-Paul.Chaput at lip6.fr> wrote:
> > 
> > On Mon, 2020-02-10 at 16:38 +0000, Luke Kenneth Casson Leighton wrote:
> > > On Mon, Feb 10, 2020 at 4:05 PM Jean-Paul Chaput
> > > <Jean-Paul.Chaput at lip6.fr> wrote:
> > > > 
> > > > 
> > > > Hello Tobias,
> > > > 
> > > > I'm a little surprised that you mention Mauka, Knik & Kite, as they should
> > > > no longer in the doc. They are replaced by Etesian/Coloquinte and Katana.
> > > > 
> > > > Did you use the "devel" branch ? If not, please do so. The "master" is
> > > > terribly late (and the new repository is https://gitlab.lip6.fr/jpc/coriolis.git)
> > > 
> > > we've got this far:
> > > https://libre-riscv.org/HDL_workflow/coriolis2/
> > > and it does include "git checkout devel"
> > > 
> > > tobias did you follow that instruction?
> > > 
> > > > Alongside with that, and my apologies for the doc to be unclear, you
> > > > will need Alliance and alliance-check-toolkit which are:
> > > > 
> > > > https://gitlab.lip6.fr/jpc/alliance.git
> > > > https://gitlab.lip6.fr/jpc/alliance-check-toolkit.git
> > > 
> > > i will add these to
> > > https://libre-riscv.org/HDL_workflow/coriolis2/
> > > 
> > > > Alliance provide additional CAD tools and some cells libraries.
> > > > Alliance Check Toolkit gives you examples and a complete Makefile
> > > > architecture to automate designs.
> > > > 
> > > > You can extract from the Dockerfile in bootstrap/docker/debian9
> > > > the scripts to install & rebuild in your schroot environement.
> > > > (also take allianceInstaller.sh and socInstaller.py).
> > > 
> > > 
> > > 
> > > > Basically you are correct, as you have Verilog you can directly
> > > > enter Yosys (providing a cell library under the form of ".lib").
> > > > Yosys do not "convert" your design, it synthesize it using the
> > > > standard cells as building block. Then you can place (Etesian)
> > > > then route (Katana). You will get a *symbolic* layout that is
> > > > to be converted in real, but that operation needs to acces the
> > > > technology which is under NDA, so it is delegated to Staf
> > > > Verhaegen.
> > > 
> > > that bit we will do later: the goal here is to do something - anything
> > > - that allows us to have some reasonably accurate time-estimates for
> > > place-and-route of libresoc modules (any libresoc modules) once
> > > "initial hurdles are completed and documented".
> > > 
> > > so we just need "something" - not under NDA - to get started.  the
> > > problem is, we don't know what we don't know, so don't know how to
> > > ask, or find what we don't know we need to ask or not ask, if you know
> > > what i mean :)
> > > 
> > > is there a chip - any chip - any project template, any project example
> > > - which "works", from start to finish (excluding NDA'd tools), using
> > > any geometry (180nm is better), that we can look at, compile
> > > unmodified, so that we can document how to do that?  then, from there,
> > > move on to looking at replacing its verilog code with our own
> > > (actually .il files from yosys more like, but that's another story)?
> > 
> >   You must create a configuration for alliance-check-toolkit:
> > 
> >     alliance-check-toolkit/etc/mk/users.d/user-LOGIN.mk
> > 
> >     where you define where the various tools are installed
> >     (look in other ones to have an idea).
> > 
> >   You can try the ARM in alliance-check-toolkit:
> > 
> >     > cd alliance-check-toolkit/benchsARM/cmos/
> >     > make lvx
> 
> ok that's happily running....
> 
> >     Should take about five minutes. It's symbolic, but should be
> >     a configuration compatible with 180nm. To actually see the
> >     results:
> > 
> >     > make cgt
> > 
> >     Then "File -> Open", "arm_chip_cts_r"
> > 
> >     To have a very rough approximation, you can say that one lambda
> >     equal 180nm.
> 
> will let you know how it goes... aw poop.
> 
>         ---> Extract symbolic figure arm_chip_cts_r
>         <--- done !
> 
>         ---> Total extracted capacitance
>         <--- 0.0pF
> MBK_SEPAR='_'; export MBK_SEPAR; /home/lkcl/alliance/install/bin/lvx
>        vst al arm_chip_cts_r arm_chip_cts_r_ext -f
> 
>                        @@@@@@      @@@@    @@@ @@@@   @@@@
>                          @@         @@      @   @@     @
>                          @@         @@      @    @@   @
>                          @@          @@    @      @@ @
>                          @@          @@    @       @@
>                          @@           @@  @        @@
>                          @@           @@  @        @@@
>                          @@            @@@        @  @@
>                          @@      @     @@@       @    @@
>                          @@     @       @       @      @@
>                        @@@@@@@@@@       @      @@@    @@@@
> 
>                              Gate Netlist Comparator
> 
>                    Alliance CAD System 5.0,            lvx 1.5
>                    Copyright (c) 1992-2020,     ASIM/LIP6/UPMC
>                    E-mail        : alliance-users at asim.lip6.fr
> 
> 
> 
> Segmentation fault
> mk/alliance.mk:53: recipe for target 'lvx-arm_chip_cts_r' failed
> make: *** [lvx-arm_chip_cts_r] Error 139
> 
> (coriolis2)lkcl at fizzy:~/alliance-check-toolkit/etc/mk/users.d$ cat user-lkcl.mk
> # Where lkcl gets his tools installeds.
> 
>  #export CORIOLIS_TOP  =
> $(HOME)/coriolis-2.x/$(BUILD_VARIANT)$(LIB_SUFFIX_)/$(BUILD_TYPE_DIR)/install
>  #export ALLIANCE_TOP  = $(HOME)/alliance/$(BUILD_VARIANT)$(LIB_SUFFIX_)/install
>  export CHECK_TOOLKIT = $(HOME)/alliance-check-toolkit
>  export YOSYS_TOP     = /usr
> 
> (CORIOLIS_TOP and ALLIANCE_TOP are already defined from the coriolisEnv)
> 
> (coriolis2)lkcl at fizzy:~/alliance-check-toolkit/benchs/ARM/cmos$
> MBK_SEPAR='_'; export MBK_SEPAR
> (coriolis2)lkcl at fizzy:~/alliance-check-toolkit/benchs/ARM/cmos$ gdb
> /home/lkcl/alliance/install/bin/lvx
> GNU gdb (Debian 7.12-6) 7.12.0.20161007-git
> Copyright (C) 2016 Free Software Foundation, Inc.
> License GPLv3+: GNU GPL version 3 or later <http://gnu.org/licenses/gpl.html>
> This is free software: you are free to change and redistribute it.
> There is NO WARRANTY, to the extent permitted by law.  Type "show copying"
> and "show warranty" for details.
> This GDB was configured as "x86_64-linux-gnu".
> Type "show configuration" for configuration details.
> For bug reporting instructions, please see:
> <http://www.gnu.org/software/gdb/bugs/>.
> Find the GDB manual and other documentation resources online at:
> <http://www.gnu.org/software/gdb/documentation/>.
> For help, type "help".
> Type "apropos word" to search for commands related to "word"...
> Reading symbols from /home/lkcl/alliance/install/bin/lvx...done.
> (gdb) set args  vst al arm_chip_cts_r arm_chip_cts_r_ext -f
> (gdb) run
> Starting program: /home/lkcl/alliance/install/bin/lvx vst al
> arm_chip_cts_r arm_chip_cts_r_ext -f
> 
>                        @@@@@@      @@@@    @@@ @@@@   @@@@
>                          @@         @@      @   @@     @
>                          @@         @@      @    @@   @
>                          @@          @@    @      @@ @
>                          @@          @@    @       @@
>                          @@           @@  @        @@
>                          @@           @@  @        @@@
>                          @@            @@@        @  @@
>                          @@      @     @@@       @    @@
>                          @@     @       @       @      @@
>                        @@@@@@@@@@       @      @@@    @@@@
> 
>                              Gate Netlist Comparator
> 
>                    Alliance CAD System 5.0,            lvx 1.5
>                    Copyright (c) 1992-2020,     ASIM/LIP6/UPMC
>                    E-mail        : alliance-users at asim.lip6.fr
> 
> 
> 
> 
> Program received signal SIGSEGV, Segmentation fault.
> mvl_y_parse () at ../../../alliance/src/mbk/src/mvl_scomp_y.y:1546
> 1546                        losig_pnt = losig_pnt->NEXT;
> (gdb) where
> #0  mvl_y_parse () at ../../../alliance/src/mbk/src/mvl_scomp_y.y:1546
> #1  0x00007ffff7bb8107 in vhdlloadlofig (
>     pt_lofig=pt_lofig at entry=0x55555575b4c0,
>     figname=figname at entry=0x55555575b4a0 "arm_chip_cts_r",
>     mode=mode at entry=65 'A') at ../../../alliance/src/mbk/src/mvl_parse.c:92
> #2  0x00007ffff7b9af23 in loadlofig (ptfig=ptfig at entry=0x55555575b4c0,
>     name=name at entry=0x55555575b4a0 "arm_chip_cts_r", mode=mode at entry=65 'A')
>     at ../../../alliance/src/mbk/src/mbk_lo_util.c:1373
> #3  0x00007ffff7b9aff1 in getlofig (fname=<optimized out>,
>     mode=<optimized out>) at ../../../alliance/src/mbk/src/mbk_lo_util.c:84
> #4  0x0000555555557967 in loadfigure (format=0x7fffffffeaaf "vst",
>     figname=0x7fffffffeab6 "arm_chip_cts_r", flag_flatten=<optimized out>)
>     at ../../../alliance/src/lvx/src/lvx.c:1615
> #5  0x000055555555529d in main (argc=6, argv=0x7fffffffe848)
>     at ../../../alliance/src/lvx/src/lvx.c:1786
> (gdb)
> 
> (gdb) print losig_pnt
> $1 = <optimized out>
> (gdb) print losig_pnt->NEXT;
> Invalid character ';' in expression.
> (gdb) print losig_pnt->NEXT
> value has been optimized out
> (gdb)
> 
> hmmm...
> 
> $ strace -o log.txt /home/lkcl/alliance/install/bin/lvx          vst
> al arm_chip_cts_r arm_chip_cts_r_ext -f
> 
> hmm... last thing: opens arm_chips_cts_r_ext.vst (attached).

  That's strange that I do not have the same problem at my end.
  My docker is build upon the latest Debian9. The only thing
  that differ is the kernel, but that shouldn't be an issue.
  I will check with your schroot procedure to see if it also
  happen to me.

  Even if lvx has failed you can use "make cgt" to at least see
  the layout (try the print function to have a nice picture ;-) )


> >   No problem. You're welcome.
> > 
> >   The doc is mostly for people who already have a background in ASICs,
> >   I will try to patch something from my lecture in VLSI to help people
> >   to orient themselves.
> 
> i know "what" to expect, from a high level, if you know what i mean.
> plus i've done PCB layout.  and gate-level design.  and electronics
> circuits.  and, and, and...

  No offense intended! In ASICs, Le Diable est dans les d├ętails!


> >   The up-to-date documentation is supplied directly in the Coriolis
> >   repository:
> > 
> >      coriolis/documentation/output/index.html
> > 
> >      The links toward the doxygen doc will be invalid a this point,
> >      but everython else works.
> > 
> >    After installation, it is put in:
> > 
> >      coriolis-
> > 2.x/Linux.x86_64/Release.Shared/install/share/doc/coriolis2/en/html/index.html
> 
> oooo.... coriolis-
> 2.x/Linux.x86_64/Release.Shared/install/share/doc/coriolis2/en/html/main/PythonTutorial
> /index.html
> 
> niiice!  that's going in the notes...

  Argh! This is still the "old" (like, one week old) version of the doc which is
  generated by sphinx. You should update (from the gitlab). It will be more
  complete, and I hope, nicer.

> l.
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-- 

      .-.     J e a n - P a u l   C h a p u t  /  Administrateur Systeme
      /v\     Jean-Paul.Chaput at lip6.fr
    /(___)\   work: (33) 01.44.27.53.99              
     ^^ ^^    cell:      06.66.25.35.55   home: 09.65.29.83.38

    U P M C   Universite Pierre & Marie Curie
    L I P 6   Laboratoire d'Informatique de Paris VI
    S o C     System On Chip


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