[libre-riscv-dev] [Bug 178] first coriolis2 tutorial, workflow and "test project" page

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=178

--- Comment #12 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Tobias Platen from comment #11)
> I've now cloned the repo and saw the first empty commit.

fantastic, ok (btw cole, you could follow this as well!  we will
update the docs accordingly)

so the next step is just to literally copy the contents of
alliance-check-toolkit/benchs/6502/cmos, minus the m65s.v file
and minus the deprecated.coriolis2 subdirectory, then, hmmm...
how about this?

create a file "example_test.py" with this in it.. i'm hacking this
together from two sources so it's untested:


from nmigen.cli import rtlil
from ieee754.part.test.test_partsig improt TestAddMod

def test(self):
    width = 16
    part_mask = Signal(4)  # divide into 4-bits
    module = TestAddMod(width, part_mask)
    sim = create_ilang(module,
                               [part_mask,
                                module.a.sig,
                                module.b.sig,
                                module.add_output,
                                module.eq_output],
                               "part_sig_add")


def create_ilang(dut, ports, test_name):
    vl = rtlil.convert(dut, name=test_name, ports=ports)
    with open("%s.il" % test_name, "w") as f:
        f.write(vl)

if __name__ == "__main__":
    test()


and add that to the (new) Makefile with a dependency "part_sig_add.il"?

global-search-replace m65s with part_sig_add...

modify the "read_verilog" command to replace it with "read_ilang"...

what do you think, tobias?

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