[libre-riscv-dev] [Bug 138] NLNet 2019 Coriolis2 Layout proposal

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=138

--- Comment #4 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
* each intern receives EUR 600 per month from LIP6.fr.
* let us assume additional costs (management, other engineers) bringing that to
EUR 1000 per month, particularly in case LIP6 interns are not available.
* let us assume 3 interns, that's EUR 3,000 per month.  around 4-6 weeks of
that will be "training".

to do the layout, we can estimate between 6-9 months of work.  a "do everything
automated and pray" is not going to work: we need to do low-level
partial-manual, partial-automated layout.

then (as you surmise, Michiel), we will run into issues with nmigen.  already,
we know for example that nmigen needs to be modified to support ASICs ("unknown
/ uninitialised" signal states). *migen* supports these, nmigen does not.  we
would like to reserve around EUR 6,000 to 8,000 for the nmigen developers.

then, Jean-Paul explained that sometimes, you actually have to modify the
verilog - small tweaking - to get it to properly in to shape for the layout. 
this will need one of the people who wrote the nmigen HDL (me, or jacob) to
take a look at it.  let us estimate 7-10 weeks here, around EUR 5,000.

so we are at around EUR 27,000 + 8,000 + 5,000 = EUR 40,000 *estimated*, hence
the reason for requesting EUR 50,000, to be on the safe side.

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