[libre-riscv-dev] [Bug 138] NLNet 2019 Coriolis2 Layout proposal

bugzilla-daemon at libre-riscv.org bugzilla-daemon at libre-riscv.org
Fri Feb 7 17:17:43 GMT 2020


--- Comment #3 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
In the NLNet project the tape-outs are foreseen to be on 180nm. I would like to
stick to that for the moment.
I would see 130nm as a possible follow-up. These tape-outs will be sponsored by
Google though, so I don't know if that is acceptable for libre-soc development.

> > This should be discussed with Staf also. This is important becausewe need that information to configure the symbolic layout for it(typically, how many metal layers, are they all usable for routingnormal wires and so on). Then we can make place & route that aresufficiently realistics.
> ok.

The process has 6 layers of metal. Metal2-Metal5 have the same
min.space/min.width design rule. Metal6 is a thick metal so needs higher pitch.
Via5 (between Metal5 and Metal6) also has bigger width and space so Metal5 will
likely need to be higher pitch.
I think it is best to discuss the exact configuration first further off-line;
exact dimensions of the technology are under NDA.

> > And lastly, there is the tricky part of writing the translation rulessymbolic to real (that is GDSII). We have tried to automate that inthe past but never finished for various non-technical reasons...This may be the occasion.
> that would be helpful, or at least know what needs to be done so itcan go on the list of tasks.

I will take care of S2R. DRC etc; of course if there is a bug in S2R I will
need support.
I am doing standard cell development and S2R may not even be needed... In the
mean time the nsxlib can be used for development of the place-and-route

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