[libre-riscv-dev] partitioned compare and mux

[Luke Kenneth Casson Leighton]

On Fri, Feb 7, 2020 at 3:24 PM Michael Nolan <mtnolan2640 at gmail.com> wrote:

> Partsig does exactly this right now, instead of negating A (which
> doesn't give the correct result anyway), it negates the output of (A==B)
> from the partitioned comparison module.

*click* and because we now do *all* bits, that works..  ok we get away
with that.

previously, because only the LSB of each partition was set, inverting
all bits of the result was't ok.

ok so i think we're good there.  would you like to tackle __neg__,
__sub__, and __invert__?  __invert__ is dead-easy, __neg__ and __sub__
will need the PartitionedAdder except perhaps doing a "subtract" mode
to it.  line 199:
https://git.libre-riscv.org/?p=ieee754fpu.git;a=blob;f=src/ieee754/part_mul_add/adder.py;h=0c28e6c4be4b6930c227b7614df025fa10399132;hb=HEAD#l199

just a mode-flag to PartitionedAdder "if self.subtract: return a - b
else return a + b"

__neg__ it maay be best to subtract from Const(0x000000000) and use
PartitionedAdder again (in "subtract" mode)

or, you never know: that might be worth testing, to see if the
principles of PartitionedAdder would work with a "~" operator as well:
i suspect that it will.

so...

class PartitionedAdder:
      ADD_MODE=0x0
      SUB_MODE=0x1
      INV_MODE=0x2

then

if self.mode == ADD_MODE:
    expanded_out.eq(self.a + self.b)
elif self.mode == SUB_MODE:
    expanded_out.eq(self.a - self.b)
 else
    expanded_out.eq(~self.a)

something like that?

do read up on how PartitionedAdder works, it saves a lot of
computation in the simulation, and when running on FPGAs, plus it's
really neat - any questions do ask, we need to document it on the
wiki.

l.