[libre-riscv-dev] [Bug 165] New: Formally verify the FPCMP (FEQ, FLE, FLT) module

[Luke Kenneth Casson Leighton]

hang on i just spotted this:
from ieee754.part_cmp.eq_gt_ge import PartitionedEqGtGe

i'll give that a shot in test_partsig.py.

l.