[libre-riscv-dev] [Bug 165] New: Formally verify the FPCMP (FEQ, FLE, FLT) module

[Michael Nolan]

Luke Kenneth Casson Leighton <lkcl at lkcl.net> writes:

>
> michael if you want something a bit challenging to do, could you see if you
> can optimise the part_cmp eq.py code?

In the truth table for partitioned EQ here
https://libre-riscv.org/3d_gpu/architecture/dynamic_simd/eq/, whenever
the partition gates are open, there are 0s in the table for some of the
outputs. Do those actually need to be 0, or can they be X's?

--Michael