[libre-riscv-dev] [Bug 165] New: Formally verify the FPCMP (FEQ, FLE, FLT) module
mtnolan2640 at gmail.com
Mon Feb 3 14:15:13 GMT 2020
Luke Kenneth Casson Leighton <lkcl at lkcl.net> writes:
> michael if you want something a bit challenging to do, could you see if you
> can optimise the part_cmp eq.py code?
In the truth table for partitioned EQ here
the partition gates are open, there are 0s in the table for some of the
outputs. Do those actually need to be 0, or can they be X's?
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