[libre-riscv-dev] PowerISA, NLNet grants

[Samuel Falvo II]

Yeah; when people say that you can have a Forth system that has "a complete
programming language, assembler, and screen editor in 8K of space!",
there's always this implied but unspoken dependency on the host
microprocessor: either a 6809 or a Z80A.  The 6502 will need closer to 11KB
for the same, and most 16/32-bit processors (TMS9900, 68000, 8086; I guess
Z8000 as well, but never measured it) will require closer to 16KB to 30KB.
A pure 32- or 64-bit processor[1] will require proportionately more space
still.  Tiny amounts of code *for those processors*, but not in absolute
terms.  ;-)

That's why when I finished DX-Forth's interpreter and block wordset for the
Kestrel-2DX, I was ecstatic that I was able to fit the interpreter,
compiler, and block I/O in about 20KB of space.  Note: no assembler, no
screen editor, etc.  ;)  I did manage to compile my "Vibe" screen editor
for it just to see how much space I'd consume, and it was pretty close to
32KB.

Oh well.

________
1.  Assuming instructions are 32-bits wide.


On Mon, Feb 3, 2020 at 12:57 PM Luke Kenneth Casson Leighton <lkcl at lkcl.net>
wrote:

> On Monday, February 3, 2020, Samuel Falvo II <sam.falvo at gmail.com> wrote:
>
> > On Mon, Feb 3, 2020 at 12:28 PM Luke Kenneth Casson Leighton <
> > lkcl at lkcl.net>
> > wrote:
> >
> > > On Monday, February 3, 2020, Samuel Falvo II <sam.falvo at gmail.com>
> > wrote:
> > >
> > > > Shucks -- sorry for the spam.  I didn't realize that went out to the
> > > whole
> > > > list.  I meant that to go to Luke privately.  Sorry!
> > >
> > >
> > > no it's fantastic, samuel.
> > >
> > > is what you are doing more compact than assembly code by chance? the
> > reason
> > > i ask is because we need a boot ROM.
> > >
> >
> > At this stage of development, no.  The Forth interpreter is partially
> > written in assembly language.
> >
> > My current port of Forth uses a 16-bit direct-threaded interpreter
> design,
> > which means that your program text cannot exceed 64KB in size,
>
>
> >
> ok, i was looking at around 8k and the SRAM maybe 16k or being the L1
> Cache.
>
> mitch described a very nice technique for pinning the L2 cache addresses at
> startup.
>
> l.
>
>
>
> --
> ---
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-- 
Samuel A. Falvo II