[libre-riscv-dev] PowerISA, NLNet grants

[Luke Kenneth Casson Leighton]

On Monday, February 3, 2020, Samuel Falvo II <sam.falvo at gmail.com> wrote:

> On Mon, Feb 3, 2020 at 12:28 PM Luke Kenneth Casson Leighton <
> lkcl at lkcl.net>
> wrote:
>
> > On Monday, February 3, 2020, Samuel Falvo II <sam.falvo at gmail.com>
> wrote:
> >
> > > Shucks -- sorry for the spam.  I didn't realize that went out to the
> > whole
> > > list.  I meant that to go to Luke privately.  Sorry!
> >
> >
> > no it's fantastic, samuel.
> >
> > is what you are doing more compact than assembly code by chance? the
> reason
> > i ask is because we need a boot ROM.
> >
>
> At this stage of development, no.  The Forth interpreter is partially
> written in assembly language.
>
> My current port of Forth uses a 16-bit direct-threaded interpreter design,
> which means that your program text cannot exceed 64KB in size,


>
ok, i was looking at around 8k and the SRAM maybe 16k or being the L1 Cache.

mitch described a very nice technique for pinning the L2 cache addresses at
startup.

l.



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