[libre-riscv-dev] [Bug 165] New: Formally verify the FPCMP (FEQ, FLE, FLT) module

[Luke Kenneth Casson Leighton]

On Monday, February 3, 2020, Michael Nolan <mtnolan2640 at gmail.com> wrote:

> Luke Kenneth Casson Leighton <lkcl at lkcl.net> writes:
>
> I don't have anything for gt/lt yet, but would something like this be
> better for eq? (I think I could modify it for gt/lt as well)
>
> https://i.imgur.com/DRMvTzR.jpg


those are full adders right?  and P0 P1 P2 go into them?


>
> The muxes are two input, and would copy the inputs straight through when
> sel is 0, and swap them when sel is 1.


 muxes right, not adders.  ok.  errr not muxes, you're describing a
crossbar.

ok so there are 3 inputs, the crossbar switcher and the outputs (2 in
crossbars are around 20 to 30 gates iirc, quite a lot, surprising)




> --Michael
>
> (also, is imgur an acceptable site for sharing images or should I put
> them somewhere else?)



i prefer in ikiwiki will upload later

l.




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