[libre-riscv-dev] [Bug 276] New: SR NAND Latch needed in nmigrn

bugzilla-daemon at libre-riscv.org bugzilla-daemon at libre-riscv.org
Fri Apr 3 11:00:37 BST 2020


            Bug ID: 276
           Summary: SR NAND Latch needed in nmigrn
           Product: Libre-SOC's first SoC
           Version: unspecified
          Hardware: Other
                OS: Linux
            Status: CONFIRMED
          Severity: enhancement
          Priority: ---
         Component: Source Code
          Assignee: lkcl at lkcl.net
          Reporter: lkcl at lkcl.net
                CC: libre-riscv-dev at lists.libre-riscv.org
   NLnet milestone: ---

The Dependency Matrices are huge and need SR NAND latches to get their size
down.  This means we need to be able to express them in nmigen, perform some
form of equivalent simulation, and also have them passed through to yosys.

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