[libre-riscv-dev] submitted bugreport to upstream nmigen
Immanuel, Yehowshua U
yimmanuel3 at gatech.edu
Thu Apr 2 19:19:07 BST 2020
> fantastic to hear that. must contact her and offer some € for nmigen
> work. in particular we need simulation of SR NAND latch and support
> for it to output into yosys.
Yes. Whitequark is great. I had contacted ‘quark some time ago about supporting her work directly.
It would be nice if we could support her work on YosysCXX too.
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