[libre-riscv-dev] submitted bugreport to upstream nmigen

[Luke Kenneth Casson Leighton]

On Thu, Apr 2, 2020 at 4:04 AM Jacob Lifshay <programmerjake at gmail.com> wrote:

> > we may just need to write our own run_simulation function for now.
>
> I created a pull request that hopefully fixes this issue and
> whitequark accepted it like 5 min later -- she's fast!

fantastic to hear that. must contact her and offer some € for nmigen
work.  in particular we need simulation of SR NAND latch and support
for it to output into yosys.