[libre-riscv-dev] power pc

[Jacob Lifshay]

On Thu, Oct 31, 2019, 12:24 Luke Kenneth Casson Leighton <lkcl at lkcl.net>
wrote:

> On Thu, Oct 31, 2019 at 7:19 PM Jacob Lifshay <programmerjake at gmail.com>
> wrote:
> >
> > well, I had intentionally wanted to map risc-v x1 to x31 to power's
> integer
> > register 1 to 31 and risc-v f0 to f31 to power's fp reg 0 to 31. that
> > allows using standard power instructions to save and restore state to
> also
> > save and restore the risc-v registers rather than needing the risc-v
> > extensions to depend on SV extending the register numbers. that also
> > simplifies the code needed to handle syscalls and (if they're are
> > implemented) inter-architecture function calls.
>
> true.  the potential issue is: if POWER overwrites registers in a
> different fashion.  RV has a single "scratch register" {x}SCRATCH
> which swaps into (one) register so that you have at least one register
> to do context-switching "stuff".
>

from reading the Power spec and Linux source, Power saves and restores all
registers in a similar fashion for interrupts (there aren't any mips-like
reserved-for-os GPRs). the important part is that they're all
saved/restored, not how they're saved/restored.

we should be able to get risc-v to work just fine by writing a new entry
point and/or using the kvm subsystem.

the power syscall entry point doesn't save everything because it's more
like a function call than an interrupt. all that's needed is for risc-v to
map to a different entry point.

Jacob