[libre-riscv-dev] power pc

Jacob Lifshay programmerjake at gmail.com
Mon Oct 28 06:54:46 GMT 2019

On Sun, Oct 27, 2019 at 10:56 PM Michael Pham <pham.michael.98 at gmail.com> wrote:
> On Sun, Oct 27, 2019 at 10:28 PM Jacob Lifshay <programmerjake at gmail.com> wrote:
> >
> > <snip>
> >
> > Power does have the necessary operations, however, because C++11's
> > memory model doesn't map simply to Power's memory fence instructions
> > and because Power doesn't have non-macro-fused atomic RMW
> > instructions, implementations have a much harder time making the
> > atomic operations efficient.
> >
> This stuff goes way over my head, but out of curiosity, does RISC-V
> have the same problem as POWER or does it map C++11's memory model
> better?

Was actually playing around with RISC-V atomics on compiler explorer
when you sent the email. :)

RISC-V maps C++11's memory model much better, mostly because it was
designed with C++11's memory model in mind.

Comparison between RISC-V, Power, and Aarch64 (ARM):

Note that the reason C++11 is important is because it's C++, and
because quite a few other languages use a memory model based on C++11:
C11, Vulkan (using VK_KHR_vulkan_memory_model), Rust, JavaScript
(using SharedArrayBuffer; supports just sequential consistency), Go
(WIP; supports just sequential consistency), WebAssembly (WIP)

Java's memory model is a subset of C++11's -- it only supports
sequential consistency (using volatile).

> >(snip)
> >
> > Jacob Lifshay
> >
> Just wanted to say you sound like an absolute genius to me :)



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