[libre-riscv-dev] power pc

[Michael Pham]

On Sun, Oct 27, 2019 at 10:28 PM Jacob Lifshay <programmerjake at gmail.com> wrote:
>
> On Tue, Oct 22, 2019 at 9:08 AM Luke Kenneth Casson Leighton
> <lkcl at lkcl.net> wrote:
> >
> > On Tuesday, October 22, 2019, Jacob Lifshay <programmerjake at gmail.com>
> > wrote:
> >
> > > On Sat, Oct 19, 2019 at 7:11 AM Luke Kenneth Casson Leighton
> > > > Jacob what's the deal with c++11 memory models? Why does that matter and
> > > > how is Power not able to cope?
> > >
> > > The problem is that Power requires quite a few expensive instructions
> > > for common atomic operations:
> > >
> > > from https://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html
> > >
> > > <snip>
> >
> >
> > Ok so they do have them. These look like they have been designed "a la
> > RISC" i.e intended to be macro op fused.
>
> Power does have the necessary operations, however, because C++11's
> memory model doesn't map simply to Power's memory fence instructions
> and because Power doesn't have non-macro-fused atomic RMW
> instructions, implementations have a much harder time making the
> atomic operations efficient.
>

This stuff goes way over my head, but out of curiosity, does RISC-V
have the same problem as POWER or does it map C++11's memory model
better?

>(snip)
>
> Jacob Lifshay
>

Just wanted to say you sound like an absolute genius to me :) Wish I
was good at this low-level hardware stuff too.

- Michael