[libre-riscv-dev] Growing a RISC-V GPU Community
Michael Pham
pham.michael.98 at gmail.com
Sun Oct 13 17:22:03 BST 2019
On Sun, Oct 13, 2019 at 8:12 AM Luke Kenneth Casson Leighton
<lkcl at lkcl.net> wrote:
>
> On Sunday, October 13, 2019, Michael Pham <pham.michael.98 at gmail.com> wrote:
>
> > Hi all,
> >
> > A while back on the mailing lists, Luke mentioned the possibility of
> > an Open 3D Graphics Alliance. So as I was taking a short break from my
> > homework, I tried to find out if anyone else is working on RISC-V
> > GPUs. Well, the good and bad news is that Libre RISC-V is dominating
> > the search results on Google when I tried to find some other RISC-V
> > GPU projects :)
> >
> > However, I found at least one other RISC-V GPU effort.
> > I think the name of it is "BaseJump Manycore", but the name isn't
> > really clear from that page so I might be wrong. Check it out:
> > https://fossi-foundation.org/2019/09/03/gsoc-64b-pointers-in-rv32
>
>
> Excellent, do you want to get in touch with them?
>
> Also add links on resources page?
>
Sure
> > I thought it would make sense for maybe Luke and Pixilica/Open 3D
> > Graphics Alliance to make a joint presentation at the next RISC-V
> > summit on custom 3D graphics extensions to the ISA. It would help to
> > spread awareness of all Libre RISC-V's proposals which could lead to
> > support for making it into the standard officially (e.g. ztrans,
> > zfpacc, etc.).
>
>
> RISCV Foundation already turned the presentation down.
>
> Yes, really.
>
You know what? The RISC-V Foundation also turned down Clifford's
presentation on the RISC-V BitManip extension...
https://twitter.com/oe1cxw/status/1175007251414863872
> > One more thing that's unrelated to graphics, is formal verification.
> > Take a look at this session description:
> > https://tmt.knect365.com/risc-v-summit/agenda/1#securityverification_
> > democratising-formal-verification-of-risc-v-processors
> >
> > Wow! They found **many** bugs in the PULP and lowRISC processors. Some
> > corner-case bugs that are almost impossible to catch through test
> > cases and simulation. This really underlines the need to find someone
> > to join the team to do formal verification of Libre RISC-V before we
> > start manufacturing thousands of possibly faulty silicone.
> >
> >
> Yyep. Now you know why we put in that application
>
I noticed you added in a name for formal proofs on the proposals page
but no description by the way.
Michael
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