[libre-riscv-dev] Growing a RISC-V GPU Community

Michael Pham pham.michael.98 at gmail.com
Sun Oct 13 09:36:18 BST 2019

Hi all,

A while back on the mailing lists, Luke mentioned the possibility of
an Open 3D Graphics Alliance. So as I was taking a short break from my
homework, I tried to find out if anyone else is working on RISC-V
GPUs. Well, the good and bad news is that Libre RISC-V is dominating
the search results on Google when I tried to find some other RISC-V
GPU projects :)

However, I found at least one other RISC-V GPU effort.
I think the name of it is "BaseJump Manycore", but the name isn't
really clear from that page so I might be wrong. Check it out:

It looks like they are under the umbrella of the FOSSi Foundation

Would it make sense to form a collaboration with them? Either directly
or through the Open 3D Graphics Alliance?

There was also something called "Hwacha". It is a vector processor but
someone mentioned that it could also be used as a GPU.

>From their slides and papers, they seem to have some good ideas that
maybe Libre RISC-V could make use of indirectly?

Finally, I was visiting the RISC-V website to take a look at the
upcoming sessions for the summit. Some groups are presenting
interesting custom ISA extensions to RISC-V such as this one:

I thought it would make sense for maybe Luke and Pixilica/Open 3D
Graphics Alliance to make a joint presentation at the next RISC-V
summit on custom 3D graphics extensions to the ISA. It would help to
spread awareness of all Libre RISC-V's proposals which could lead to
support for making it into the standard officially (e.g. ztrans,
zfpacc, etc.).

Based on the Google results, Libre RISC-V is the *most* notable effort
to use RISC-V for graphics processing. So it makes sense for us to
nurture the seeds of a RISC-V GPU community which could possibly help
us out in the future. I think I saw that you guys were planning on
going to FOSDEM so that's a good start. Next milestone: RISC-V Summit

One more thing that's unrelated to graphics, is formal verification.
Take a look at this session description:

Wow! They found **many** bugs in the PULP and lowRISC processors. Some
corner-case bugs that are almost impossible to catch through test
cases and simulation. This really underlines the need to find someone
to join the team to do formal verification of Libre RISC-V before we
start manufacturing thousands of possibly faulty silicone.

Ok, I'm going back to my actual homework now.


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