[libre-riscv-dev] [Bug 139] Add LD.X and ST.X? Strided

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=139

--- Comment #15 from Jacob Lifshay <programmerjake at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #14)
> Is that MV.swizzle you mean, for macro op fusion? and FMV.swizzle
> 
> R4 types are a pig, they take an entire major opcode (or, funct3 so 8 of
> them, only). Even I type is big. Need to be really really certain there's
> benefit to using them.
> 
> F int times reg imm swizzle where both ops are either I type or R type
> that's 4 funct3 minor ops, and if using the RVV Major opcode we already have
> SV.setvl so that leaves only 3 funct3 minor opcodes left.
> 
> I type does 12 bit immed so yes could be used.
> 
> Like the pi idea.
> 
> New 3 reg format doable by using RVC encoding, or 4 3 3 for rd rs1 rs2.

So, how about this:

+-----------+-------+-------+-------+-------+-------+------+
|           | 31:27 | 26:25 | 24:20 | 19:15 | 14:12 | 11:7 |
+===========+=======+=======+=======+=======+=======+======+
| swizzle2  | rs3   | 00    | rs2   | rs1   | 000   | rd   |
+-----------+-------+-------+-------+-------+-------+------+
| fswizzle2 | rs3   | 01    | rs2   | rs1   | 000   | rd   |
+-----------+-------+-------+-------+-------+-------+------+
| swizzle   | 0     | 10    | rs2   | rs1   | 000   | rd   |
+-----------+-------+-------+-------+-------+-------+------+
| fswizzle  | 0     | 11    | rs2   | rs1   | 000   | rd   |
+-----------+-------+-------+-------+-------+-------+------+
| swizzlei  | imm                   | rs1   | 001   | rd   |
+-----------+                       +-------+-------+------+
| fswizzlei |                       | rs1   | 010   | rd   |
+-----------+-------+-------+-------+-------+-------+------+

Note it's the equivalent of 3 I-type instructions (with a bit of spare space
next to [f]swizzle).

the element size would be specified using the SVPrefix encodings or a similar
mechanism. Since swizzle is close to useless as a scalar instruction, the
opcode space can be shared with instructions that can't/shouldn't be
vectorized.

[f]swizzle2i is left for longer instruction formats if needed.

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