[libre-riscv-dev] [Bug 139] Add LD.X and ST.X? Strided

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=139

--- Comment #14 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
Is that MV.swizzle you mean, for macro op fusion? and FMV.swizzle

R4 types are a pig, they take an entire major opcode (or, funct3 so 8 of them,
only). Even I type is big. Need to be really really certain there's benefit to
using them.

F int times reg imm swizzle where both ops are either I type or R type that's 4
funct3 minor ops, and if using the RVV Major opcode we already have SV.setvl so
that leaves only 3 funct3 minor opcodes left.

I type does 12 bit immed so yes could be used.

Like the pi idea.

New 3 reg format doable by using RVC encoding, or 4 3 3 for rd rs1 rs2.

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