[libre-riscv-dev] nmigen uninitialized bits proposal

[Luke Kenneth Casson Leighton]

On Wed, Nov 20, 2019 at 4:30 PM Jacob Lifshay <programmerjake at gmail.com> wrote:
>
> Luke asked me to mention that there's been a lot of changes in nmigen one
> of which is that nmigen is working on getting support for uninitialized
> memory, which is needed for asics and some fpgas.

ah yeah, we'll definitely need that :)

> My proposal for bit-level uninitialized value tracking:
> https://github.com/m-labs/nmigen/pull/270#issuecomment-555598910

ah, excellent.

> See also later comments about the benefits/drawbacks of exact compatibility
> with Verilog X-propagation.