[libre-riscv-dev] nmigen uninitialized bits proposal

[Jacob Lifshay]

Luke asked me to mention that there's been a lot of changes in nmigen one
of which is that nmigen is working on getting support for uninitialized
memory, which is needed for asics and some fpgas.

My proposal for bit-level uninitialized value tracking:
https://github.com/m-labs/nmigen/pull/270#issuecomment-555598910

See also later comments about the benefits/drawbacks of exact compatibility
with Verilog X-propagation.

Jacob Lifshay