[libre-riscv-dev] Fwd: RISC-V Hypervisors
Luke Kenneth Casson Leighton
lkcl at lkcl.net
Thu May 30 12:11:38 BST 2019
On Thu, May 30, 2019 at 11:12 AM Jacob Lifshay <programmerjake at gmail.com> wrote:
> If we have everything but nested page tables handled by M-mode traps,
> then we can always follow changing specs by updating the M-mode code.
> One part I just realized that may need additional HW acceleration is
> handling interrupt routing.
it sounds like we need to keep track of this properly. can you raise
a bugreport, put some links (to the archives) so it's not lost as
noise, and can we move the discussion to the bugtracker?
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