[libre-riscv-dev] Fwd: RISC-V Hypervisors

[Jacob Lifshay]

If we have everything but nested page tables handled by M-mode traps,
then we can always follow changing specs by updating the M-mode code.
One part I just realized that may need additional HW acceleration is
handling interrupt routing.

On Thu, May 30, 2019 at 3:09 AM Luke Kenneth Casson Leighton
<lkcl at lkcl.net> wrote:
>
> On Thu, May 30, 2019 at 10:55 AM Jacob Lifshay <programmerjake at gmail.com> wrote:
> >
> > I think it would be a good idea to implement hypervisor extensions,
>
>  it would be pretty neat, agreed, particularly if it's straightforward
> enough to do, and well-defined.
>
> l.
>
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