[libre-riscv-dev] [Bug 87] investigate scoreboard global write pending change

bugzilla-daemon at libre-riscv.org bugzilla-daemon at libre-riscv.org
Sat May 25 21:27:00 BST 2019


http://bugs.libre-riscv.org/show_bug.cgi?id=87

--- Comment #1 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
https://groups.google.com/d/msg/comp.arch/LXWtd1L9JoY/7P7yifihBQAJ

Multi-issue should begin with the current state of the Read reservations and 
of the write reservations (and the FU_busy). 

As each instruction is considered for issue, you take its read reservations 
and OR it onto the current read reservations, and likewise for the write 
reservations. 

Thus, by the time you decide to issue {1,2,3,4,5} you already HAVE the 
read and write reservations for that FU you are issuing into transitively 
through the whole set of issuing instructions. 

1-issue just uses the current read and write reservations 
2-issue uses the current for inst 1 and current OR inst 1 reservations for 
        inst 2. 
3-issue uses the current for inst 1 and current OR inst 1 reservations for 
        inst 2 and current OR inst 1&2 reservations for inst 3 
4-issue uses the current for inst 1 and current OR inst 1 reservations for 
        inst 2 and current OR inst 1&2 reservations for inst 3 and current 
        OR inst 1&2&3 for inst 4 
5-issue uses the current for inst 1 and current OR inst 1 reservations for 
        inst 2 and current OR inst 1&2 reservations for inst 3 and current 
        OR inst 1&2&3 for inst 4 and current OR inst 1&2&3&4 for inst 5 

Thus, 5-issue is only 1 gate <delay> harder than 1-issue over where one is 
keeping track of data and control flow dependencies.

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