[libre-riscv-dev] [hw-dev] Re: 6600-style out-of-order scoreboard designs (ariane)

[Luke Kenneth Casson Leighton]

On Mon, May 20, 2019 at 5:38 PM Mitchalsup <mitchalsup at aol.com> wrote:

> > does the addition to the Computation Unit of a Read_Release_Request
> > signal look about right to you?  it's mirrored on the write release
> > request (except without the timing delay).
>
> No, what looks right to me is that readable cannot be asserted unless Issue_FU
> has taken place.

 that's why i brought in the busy signal from the CU, because it's
based on the latch which went HI when, yes, Issue took place.

> And readable goes away on detection of GO_Read_FU.

 it does... i won't bore you with the sheer volume of random
drunken-walk variations i tried

 i found that if only the "CU Busy" signal is used to switch off an
individual unit going into the priority picker, that just (spuriously)
results in re-assertion on the next clock cycle, which then re-asserts
GO_Read on the next, which causes it to be de-asserted again: flip
(bounce) flop (bounce), flip (bounce)

 this is for the FU-Deps Matrix version btw

 what i found was, because only one bit of the FU-Deps "row"
(representing src or dest regs in unary) is set, once the Latch for
that register goes LO, the "pending" dependencies are viewed as
CLEARED.

 this *reasserts* the "readable" flag... *even though the row of
dependency cells has done its job*.  result: flip-flopping of the
Go_Read flag.

 by taking the *computation unit's* SR-Latches, which are *definitely*
switched off when the Go_Read is asserted, the spurious flip-flopping
stops.


> This is what the 4-input to the 8 decoder NAND gates is supposed to do.

 sorry, am slightly confused: i'm not using NAND gates anywhere, only
AND, OR, NOT AND NOR, i haven't seen NAND anywhere in the diagrams.

 did you mean the priority picker?

l.