[libre-riscv-dev] [hw-dev] Re: 6600-style out-of-order scoreboard designs (ariane)

Luke Kenneth Casson Leighton lkcl at lkcl.net
Mon May 20 05:24:34 BST 2019

hiya mitch, just a quick update on progress.

in my random-wandering modifications i noticed that when the read
hazards are entirely clear (which can be when each FU is idle) the big
NOR readable signal(s) can be *true*.  this then causes all of the
read priority pickers to go into permanent-selection of the highest
priority FU, even if it's idle.

does the addition to the Computation Unit of a Read_Release_Request
signal look about right to you?  it's mirrored on the write release
request (except without the timing delay).

secondly, i finally figured out the significance of the major-minor
clock cycles on the FU-Regs Dependency Cell.  holy cow is it elegant,
efficient, and scary at the same time.

the key that i previously missed is that when the clock is LOW, the
"Reset" on the SR Latch is *disabled*, allowing the incoming Go_Read
to be ANDed with the Q state of the SRLatch, to generate the "Register
Select" signal for the brief [half] cycle needed to tell the Register
File "you can write now" (or read).

on the major clock cycle (half a clock cycle later), with the Go_Read
still being asserted, the latch will be reset because the combination
of the AND of the clock line plus the Go_Read will cause the Reset of
the Latch.

emulating this in "modern" design i believe is going to need something
insane like 30 gates: three DFFs, 4 MUXes at least.  where the 6600
has only 6 gates, one of those being a 3-input AND so a total of only
around 13 transistors.

just incredible.

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