[libre-riscv-dev] chinese sponsor, looking to design an ECP5-based dev board

Samuel Falvo II sam.falvo at gmail.com
Tue May 7 02:48:55 BST 2019

On Mon, May 6, 2019 at 6:26 PM Luke Kenneth Casson Leighton
<lkcl at lkcl.net> wrote:
>  that was the idea... as long as it doesn't interfere with the primary
> scope, which is that this is a board *specifically* being designed to
> accelerate *our* completion timescales.

Yeah, that's why I thought I'd throw it out to be considered, but it's
not a super high priority.  If you do manage to offer it, though, I
would definitely advocate having no fewer than 50 accessible I/Os,
even if high-density or metric connectors are used.  50 seems to be
the magic number for implementing minimal but usable backplane buses
(Zorro-III, PCI, and 16/32-bit Wishbone all seems to fall under the 50
pin threshold).

Samuel A. Falvo II

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