[libre-riscv-dev] chinese sponsor, looking to design an ECP5-based dev board

[Luke Kenneth Casson Leighton]

On Tue, May 7, 2019 at 1:25 AM Jacob Lifshay <programmerjake at gmail.com> wrote:
>
> I was thinking of having the two SO-DIMM sockets stacked vertically,
> like in: http://web.archive.org/web/20190507001733/https://avadirect-freedomusainc1.netdna-ssl.com/Pictures/500/5003581_6.png

 it's hard to tell from those overhead pictures: those are the
30-or-so-degree angled sockets.

 i do know the ones you mean.  similar to DIMMs you see normally on
servers, with the clips.

 the scope is basically that these chinese sponsors, who make some
popular embedded computing SBCs in credit-card-sized form-factor, want
to help us accelerate the development cycle of our SoC, so that they
can start selling RISC-V embedded computers.

 to be absolutely clear: they're going to make a development board
*specifically* to help *us*.  this is around a USD $15k-$20k
investment for them as a way to get our SoC out the door faster.

 stepping outside of that scope makes me uncomfortable even to attempt
to have that conversation with them.

 now, if they had said that they wanted an x86-style "NUC", or a
Micro-Server style processor, SO-DIMMs and ECC would be appropriate
things to discuss with them.

 the reality is that their experience is in these *small* very simple,
low power "embedded" designs.

 what has usefully come out of this discussion is that the ECP5 can
handle a 64-bit memory bandwidth.  *hypothetically* we *may* be able
to push the HyperRAM (out of JEDEC spec) to a 200mhz clock rate, which
would give us DDR 400mhz per 8-bit HyperRAM interface.

 even doing that, we're still only going to reach 3200 mbytes/sec,
which is still half of a 64-bit 800mhz twin-LPDDR3x32 RAM bank.

 oh.  hang on.  we might need some of the generic IDDR pins for the HyperRAM.

 72-32 = 40.... so we may only be able to do up to 5x HyperRAM
interfaces.  4x if one of the IDDR sets is allocated to eMMC.

hmmm....