[libre-riscv-dev] [Bug 74] preliminary exploratory software emulation of FP SQRT

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=74

--- Comment #41 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Aleksandar Kostovic from comment #40)

> Done this from FPU verilog code, but i still dont know how i would integrate
> it better.
> 
> Can anyone help out?

 i added some comments that will help you to transition it from the
 IEEE754 format that z is in, into s/e/m format.

 basically bit 31 is s, bits 0..22 are the mantissa, and 23 to 30 are the
 exponent.

 also the IEEE754 format adds 128 to the exponent.

 by working in that 32-bit format, you have nothing that can be returned
 from that function.

 so you need to *translate* the z-stuff *back* into s / e / m and i've
 provided some comments which will allow you to do that.

-- 
You are receiving this mail because:
You are on the CC list for the bug.