[libre-riscv-dev] Introduction

[Samuel Falvo II]

It's OK; I should be subscribed properly to the list now.

On Thu, May 2, 2019 at 5:38 PM Luke Kenneth Casson Leighton <lkcl at lkcl.net>
wrote:

> doh, forgot the cc.... sorry samuel!
>
>
> ---------- Forwarded message ---------
> From: Luke Kenneth Casson Leighton <lkcl at lkcl.net>
> Date: Fri, May 3, 2019 at 1:37 AM
> Subject: Re: [libre-riscv-dev] Introduction
> To: Libre-RISCV General Development <libre-riscv-dev at lists.libre-riscv.org
> >
> Cc: Libre-RISCV General Development <libre-riscv-dev at lists.libre-riscv.org
> >
>
>
> ---
> crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68
>
> On Thu, May 2, 2019 at 7:29 PM Samuel Falvo II <sam.falvo at gmail.com>
> wrote:
> >
> > On Thu, May 2, 2019 at 10:39 AM Luke Kenneth Casson Leighton <
> lkcl at lkcl.net>
> > wrote:
> >
> > > the project has a charter, we do make an effort to honour it :)
> > > https://libre-riscv.org/charter/discussion/
> >
> >
> > Thanks for this; it seems pretty common sense and is quite agreeable.
>
>  logical, rational, and also designed on some of the best resources i
> could find on goal-focussed organisations / community.
>
> > I feel I'm perhaps most useful with respect to 53000-related concerns;
> I'm
> > willingly going to abstain from libre-riscv issues for now, at least
> until
> > I learn more about its history and rationale.
>
>  sounds reasonable.
>
>
> http://chiselapp.com/user/kc5tja/repository/kestrel-3/artifact/96ea88450c1a3fc6
>
>  ha! you incorporated the conversion from verilog-formal to
> nmigen-formal, already, ha! :)
>
>  hey... ah...
>
> http://chiselapp.com/user/kc5tja/repository/kestrel-3/artifact/5c470620924b19d7
>
>  is that... are you storing *only* the modifiable bits, to save gates?
>  if so, cool!
>
>
>  btw:
>     for i in range(0, self.o_dat.nbits):
>
>  that can be just
>    for i in range(self.o_dat.nbits):
>
> and:
> self.bits = Signal(len(self.retained_bits))
>
>             j = 0
>             for i in range(0, self.o_dat.nbits):
>                 if i in self.retained_bits:
>                     m.d.sync += self.bits[j].eq(self.i_dat[i])
>                     j = j + 1
>
> can be arranged as:
>
> def elaborate(...)
>    i_bits = []
>    for i in self.retained_bits:
>        bits.append(self.i_dat[i])
>    i_bits = Cat(*bits)
>    with m.If(self.o_valid & self.i_we):
>         m.d.sync += self.bits.eq(bits)
>
> (1) the key there is, you don't need to walk the length of o_dat.nbits
> to get an index which you then check to see if it's in
> self.retained_bits...  *just iterate the retained_bits*
>
>  :)
>
> (2) Cat is awesome, and the graphviz is (yosys "show") is way *way*
> cleaner than doing a sequence of eqs on individual bits.
>
>
> you can do the same trick with the other loop, however yeah j still
> has to stick around.
>
>         j = 0
>         o_bits = []
>         for i in range(self.o_dat.nbits):
>             if i in self.retained_bits:
>                 o_bits.append(self.bits[j])
>                 j = j + 1
>             else:
>                 o_bits.append(C(0,1))
>             m.d.comb += self.o_dat.eq(Cat(*o_bits))
>
> there's proooobably.... there's probably a way to get that down
> somewhat (getting rid of j) by using "yield from", moving it to a
> function...
>
>        def something_like_this():
>          for i in range(self.o_dat.nbits):
>            if i in self.retained_bits:
>                 yield from self.bits
>             else:
>                 yield C(0,1)
>         o_bits = Cat(*list(something_like_this()))
>         m.d.comb += self.o_dat.eq(o_bits)
>
> maybe you can get those last two on one line, maybe don't need the
> conversion to a list, maybe make the function name shorter...
>
>        def bits_gen():
>          for i in range(self.o_dat.nbits):
>            if i in self.retained_bits:
>                 yield from self.bits
>             else:
>                 yield C(0,1)
>         m.d.comb += self.o_dat.eq(Cat(*bits_gen())
>
> which starts to look a lot cleaner.  attached file.
>
> btw... try this before and after, then do yosys read_ilang memcsr2.il
> and "show MemCSR"
> python3 mod_common_csr.py MemCSR generate -t il > memcsr2.il
>
> and compare it to what you get without the above modifications - the
> difference is quite shocking.
>
> l.
>


-- 
Samuel A. Falvo II