[libre-riscv-dev] Fwd: Preparations The Libre-RISCV SoC

[Jacob Lifshay]

On Sat, Mar 30, 2019, 08:44 Aleksandar Kostovic <
alexandar.kostovic at gmail.com> wrote:

> >
> > ok so good news here, we pass the 2nd criteria stage, now it goes
> > through to an independent review.
>
> Thats awesome! Congratulations to all of us! :)
>
likewise

>
>  we will need a one-paragraph
> > summary of the project.
>
>
> here's mine idea quick idea(idk if it should be any longer or shorter):
>
looks good to me, editing for grammar fixes & stuff

>
> //--------//
> The Libre-RISCV SoC is an ongoing development project which aims to
> fulfill the spot for a libre low-power System on a Chip - SoC capable of
> running a full operating system. Our main goal is to design a chip based on
> the open-source RISC-V ISA. Our project is fully open both in terms of
> development discussions and
> code. We will provide the source code of the SoC and its peripherals. The
> SoC
> would have the following features:
> - Four custom 64-bit cores based on the RISC-V ISA
> - GPU capable of rendering at 1280x720 resolution at 25 FPS, with a fill
> rate of 100M pixels/sec, capable of rendering 30M triangles/sec, and has
> 5-6 GFLOPS of computing power.
> - IEEE 754-2008 compliant FPU
> The source code of the SoC is written in nMigen(
> https://github.com/m-labs/nmigen), a python library for building digital
> hardware.
> We are planning on designing the chip to have a TDP of just under 2.5
> Watts,
> when manufactured on a 28nm process.
> The graphics driver of the SoC is intended to be Kazan(
> https://salsa.debian.org/Kazan-team/kazan), a Vulkan driver that
> supports cross-platform rendering, is written in the Rust programming
> language, and uses LLVM for shader compilation.
>  //--------//
>

Jacob

>