[libre-riscv-dev] IEEE754 FPU turning into ALU with Reservation Stations

Luke Kenneth Casson Leighton lkcl at lkcl.net
Thu Mar 28 23:22:07 GMT 2019

so i took a look at fmul.py, and compared it to the code in fadd, and,
aleksander, i absolutely agree with you: it's really *really* hard to
understand what's going on.

that is officially Not Good (tm).

i think i may have a way to put the Stage/Pipeline API transparently
behind this:

i appreciate that hypothetically, all of the code that's not related
to fadd, fmul, fdiv etc. could be moved to a separate python module,
which would greatly reduce the amount of code seen in each of fadd,
fmul etc. because the normalisation, packing, etc., that's all exactly
the same.

this would leave the specialcases and the actual work (mul/div/add) in
the module, making it more obvious what's going on...

... i still don't like it.  the reason is: the setup and connectivity
between stages is sufficiently involved that it's hiding actual code.
however, SimplePipeline shows that this doesn't have to be the case.

i.e. all the pipeline stage setup can be *completely automated* with
the right infrastructure.

i just have to work out what that is.


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