[libre-riscv-dev] nmigen memory

[Luke Kenneth Casson Leighton]

On Sat, Mar 23, 2019 at 6:44 AM Jacob Lifshay <programmerjake at gmail.com> wrote:

> On Fri, Mar 22, 2019, 23:30 Luke Kenneth Casson Leighton <lkcl at lkcl.net>
> wrote:

> > * setting "sychronous=False" causes a failure
> > * setting the read address early causes a failure
> > * failing to set the write-enable back to zero causes a failure
> > * failing to allow the clock to run for one cycle where write-enable
> > is high causes a failure
> >
> I think what's happening is that this is a spurious test case pass due to
> not waiting long enough after the last clock edge for data to propagate and
> getting the data from address 0 from each read port from the previous clock
> cycle since the read port's address defaults to 0. try adding a "yield
> Delay(1e-7)" before the two asserts to give time for the results to
> propagate, where 1e-7 is a non-zero fraction of the clock period. Delay is
> in nmigen.back.pysim.

sounds about right: the attached passed after inserting sufficient
yield statements (delays).

this test has 2 separate processes, one reading/writing to read port 0
and write port 0, the other reading/writing from read port 1 and write
port 1.

l.