[libre-riscv-dev] buffered pipeline

[Jacob Lifshay]

On Fri, Mar 22, 2019, 23:30 Luke Kenneth Casson Leighton <lkcl at lkcl.net>
wrote:

> this works, jacob: i took a look at the unit test test_simulation.py
>
> (btw can i recommend using run_simulation, it does exactly the same job?)
>
> key differences:
>
> * moved the explicit combinatorial setting of the ports outside to a
> time-sync'd setup
> * removed the "synchronous=False" argument
> * set the write-enable to zero *AFTER* writing
> * then set the read address
>
> this now passes.
>
> * setting "sychronous=False" causes a failure
> * setting the read address early causes a failure
> * failing to set the write-enable back to zero causes a failure
> * failing to allow the clock to run for one cycle where write-enable
> is high causes a failure
>
I think what's happening is that this is a spurious test case pass due to
not waiting long enough after the last clock edge for data to propagate and
getting the data from address 0 from each read port from the previous clock
cycle since the read port's address defaults to 0. try adding a "yield
Delay(1e-7)" before the two asserts to give time for the results to
propagate, where 1e-7 is a non-zero fraction of the clock period. Delay is
in nmigen.back.pysim.