[libre-riscv-dev] buffered pipeline
Luke Kenneth Casson Leighton
lkcl at lkcl.net
Sat Mar 23 04:54:13 GMT 2019
crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68
On Sat, Mar 23, 2019 at 1:10 AM Jacob Lifshay <programmerjake at gmail.com> wrote:
> On Fri, Mar 22, 2019 at 1:46 AM Jacob Lifshay <programmerjake at gmail.com>
> > implemented rc4, but I'm getting a test failure, will debug in the morning
> nmigen appears to not support simulation of memory with multiple write
> ports: https://github.com/m-labs/nmigen/issues/47
> no wonder my rc4 implementation was failing.
okaay, so we have our first candidate that would justify donations to
the nmigen team.
can you back-port it to migen and see if that works?
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