[libre-riscv-dev] Questions The Libre-RISCV SoC

[Aleksandar Kostovic]

I agree with all the answers you gave. I like it very much. Its a green
light from me :)

On Thu, Mar 21, 2019, 12:26 lkcl <luke.leighton at gmail.com> wrote:

> ok so as you can see, michiel got back to me, so i propose to reply as
> below.  we agreed a cutoff of 48-72 hours, i'd feel more comfortable
> if we got back to michiel within under 48, if practical.
>
> given that this could turn into an ongoing discussion (the agreement
> of milestones, below), we may have to rethink.  first bit, though:
> please do review below, comment *above* (not inline) and let me know
> if it's ok.
>
>
> On Thu, Mar 21, 2019 at 7:32 AM Michiel Leenaars <michiel at nlnet.nl> wrote:
> >
> > Dear Luke,
> >
> > just a short clarifying question: while the larger project expects to
> > have the outcome of a fully-functioning quad-core 800mhz RISC-V, the
> > effort we would fund would basically cover the FPGA pre-implementation?
>
>  yes.  i have a potential client for whom the milestone of achieving
> an FPGA implementation is a key trigger for further investment.
> NLnet's help would be a welcome financial bridge.
>
> > Or are there additional results included in the project you can commit
> to?
>
>  we have received an additional offer (separate from the potential
> client) of a donation sufficient to cover the cost of MVP
> (Multi-Vendor Programme).  if it is practical for us to move forward
> to doing the actual ASIC layout using libre VLSI tools, we will start
> that as well.
>
>  however it's not something that we can definitively commit to, as the
> layout is itself a massive task, as is the task of reaching an FPGA
> pre-implementation.
>
> > I assume you are aware that we would pay progressively as milestones are
> > reached.
>
>  appreciated.  then we will need to come up with some suitable
> milestones, otherwise there would be only the one "end" milestone
> (FPGA demo) and it would be rather... challenging.  off the top of my
> head i can think of the following tasks:
>
> * an IEEE754 floating point pipeline
> * a basic processor core (we need a management / low-power-mode / boot-up
> core)
> * a nmigen pinmux (for peripheral multiplexing)
> * a Virtual Memory Management system suitable for hybrid CPU / GPU usage
> * a software simulator compliant with the latest SimpleV Vectorisation
> Standard proposal
> * design and software simulation of some of the 3D custom instructions
> needed for the GPU
> * Kazan 3D's software SPIR-V to LLVM compiler being operational and
> running OpenCL applications (although this is also a massive task so
> may need further subdivision)
>
> there are actually a significant number of sub-tasks, many of which
> are already underway and/or have been planned in advance: we can track
> them using http://bugs.libre-riscv.org if that would work?
>
>
> http://bugs.libre-riscv.org/buglist.cgi?component=Milestones&list_id=40&product=Libre%20Shakti%20M-Class&resolution=---
>
> > Is Jacob aware of the project proposal?
>
>  yes: as is the whole team. as mentioned earlier we discussed the
> proposal and agreed how to respond when you got back to us:
>
> http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2019-February/000625.html
>
> > How do you see the division of
> > funding between him and you, and others?
>
> our Charter requires that everyone is equitably rewarded for their
> contributions:
> https://libre-riscv.org/charter/discussion/
>
> so we will strike a balance between the individual needs of each team
> member and how their contribution, if encouraged and so empowered,
> will help move the goal forward.
>
> these are for full-time focus:
>
> * i need around USD $1200-1500 per month for living expenses
> * jacob needs around $1000 per month.
>
> we've not yet had anyone else come forward to formally discuss any
> financial needs in exchange for an agreed contribution.  we do have
> the option of allocating shares (yet to be fully discussed, i am
> leaning towards http://slicingpie.com as it is about the only fair
> equitable startup calculator available).
>
> i have also contacted the nmigen developers and provisionally offered
> them a donation, as we are taking up their time with support
> questions, and using code that they spent time and resources
> developing, so it is only fair and reasonable to make sure that
> they're fairly compensated for their efforts.
>
> would that be something that could be arranged and discussed?  if it
> cannot be arranged through NLnet i feel strongly obligated to arrange
> a donation to the nmigen developers through some other means.
>
> also, since writing the proposal we have located a suitable low-cost
> FPGA developer board (around $200) called the ECP5 that happens to be
> compatible with libre-licensed toolchains.  at the appropriate point,
> a case could be made to get some of these for the team.  although they
> are smaller than the resources needed to run the full FPGA core (for
> which I have the Xilinx ZC-706), the ECP5 will manage sub-tasks very
> nicely.  and, crucially, will not need payment of FPGA SDK licensing
> fees.
>
> l.
>
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