[libre-riscv-dev] Questions The Libre-RISCV SoC

[lkcl]

hi michiel, we agreed a few weeks ago to review questions that NLnet
might have, as a group:
http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2019-February/000625.html

so after reading the guide, we're aware that you need a swift response
and will get back to you rapidly.

l.

On Thu, Mar 21, 2019 at 7:32 AM Michiel Leenaars <michiel at nlnet.nl> wrote:

> Dear Luke,
>
> just a short clarifying question: while the larger project expects to
> have the outcome of a fully-functioning quad-core 800mhz RISC-V, the
> effort we would fund would basically cover the FPGA pre-implementation?
> Or are there additional results included in the project you can commit to?
>
> I assume you are aware that we would pay progressively as milestones are
> reached.
>
> Is Jacob aware of the project proposal? How do you see the division of
> funding between him and you, and others?
>
> Thank you very much for your swift reply.
>
> Kind regards,
> on behalf of NLnet foundation,
>
> Michiel Leenaars
> Strategy Director
> +31 6 27 050 947
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