[libre-riscv-dev] buffered pipeline

[Luke Kenneth Casson Leighton]

On Mon, Mar 18, 2019 at 5:38 PM Jacob Lifshay <programmerjake at gmail.com> wrote:
>
> On Mon, Mar 18, 2019, 10:34 Luke Kenneth Casson Leighton <lkcl at lkcl.net>
> wrote:
>
> >  so a "temporary" signed/unsigned Signal could be created within the
> > process() function *and not added to the object*.
> >
> you still need to at least pass in the module otherwise you have a signal
> you can't assign to, assuming process() returns a Value.

 returns a list of nmigen statements... oh, yes, which all base-class
to a nmigen Value, yes i see what you mean.

 true... forgot about that.  exception: when the Stage class is itself
a module (and has its own elaborate), in which case its module m may
be made a member of the python class, and the intermediate / local
(signed/unsigned) may use the self.m of the Stage class instance.

 given that i was thinking along the lines of ensuring that the
pipeline logic (ready/valid etc.) is thoroughly separated from the
stage logic by doing exactly that (putting the stage logic into an
nmigen module)...

 some of the IEEE754 stages are quite involved, so it makes sense there.

 also, if using the pipeline stage to cover all of the ALU functions
(as opposed to just the one) it makes sense to isolate the buffer
functionality from the ALU functionality via modules, as well.

 btw couple of things:

 (a) could you (and everyone) do a bit more "trimming" of reply
context here, i found i had a hell of a job using a smartphone to
interact on the mailing list the past couple days, as the mobile
version of gmail doesn't hide anything, it shows the *entire* reply
and it was a pain to find anything.

 (b) i just did a translation of the simple_pipeline.py into the code
i'm working on, got it to conform to the same "API", and was able to
pass in a Stage instance, unmodified.  could you take a quick look?
 https://git.libre-riscv.org/?p=ieee754fpu.git;a=blob;f=src/add/example_buf_pipe.py;hb=HEAD#l287

thx jacob.

l.