[libre-riscv-dev] buffered pipeline

[Jacob Lifshay]

On Mon, Mar 18, 2019, 10:34 Luke Kenneth Casson Leighton <lkcl at lkcl.net>
wrote:

> ---
> crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68
>
> On Mon, Mar 18, 2019 at 4:10 PM Jacob Lifshay <programmerjake at gmail.com>
> wrote:
> >
> > On Mon, Mar 18, 2019, 05:19 Luke Kenneth Casson Leighton <lkcl at lkcl.net>
> > wrote:
>
> > > so it's a little different from the pipeline example you created,
> > > jacob, in that there's no need for explicit mention of or involvement
> > > of combinatorial logic, no module needs to be set up and so on.
> > >
> > I think that's fine, but we still need a way to have intermediate Signals
> > in our pipeline stage, since that's the only way to convert the
> > intermediate value to signed. See the implementation of alu.py sra/srl
> and
> > slt/sltu for examples where that is necessary.
>
>  oh: you might not be aware, it's perfectly possible to create a
> Signal instance in a local function, and assign to it and use it
> within that function.  at the verilog / ilang level it will get
> assigned globally to the module, however at the python level it's a
> local scoped object.
>
>  so a "temporary" signed/unsigned Signal could be created within the
> process() function *and not added to the object*.
>
you still need to at least pass in the module otherwise you have a signal
you can't assign to, assuming process() returns a Value.

>
> > >
> > > it's taking advantage of the features of python, by passing around
> > > (and returning) nmigen HDL fragments, rather than actually having the
> > > python code *do* the nmigen m.d.comb += in an explicit fashion: that's
> > > handled by the *base* class, such that the writer of the Stage doesn't
> > > have to.
> > >
> > > so in test_pipeline.py:
> > >
> > >             def elaborate(self, platform: Any) -> Module:
> > >                 m = super().elaborate(platform)
> > >                 m.d.comb += self.comb_output.eq(self.comb_input + 1)
> > >                 return m
> > >
> > > that could be removed and replaced with this in the base class:
> > >
> > >             def elaborate_more(self, platform: Any) -> Module:
> > >                 m = self.elaborate(platform)
> > >                 m.d.comb +=
> > > self.comb_output.eq(self.process(self.comb_input)
> > >                 return m
> > >
> > actually, it needs to be named elaborate since that's the name of the
> > function called by nmigen when you pass this class as an object to
> nmigen.
> > eg:
> > m.submodules.add = AddStage() # nmigen calls elaborate for us
>
>  yehyeh - you get the idea.
>
> > >
> > > or actually just combine the m.d.comb line directly into
> > > SimpleStage.elaborate() and then create a process function like this:
> > >
> > >             def elaborate(self, i):
> > >                 return i+1
> > >
> > assuming you meant def process()
>
>  yes.
>
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