[libre-riscv-dev] IEEE754 FPU turning into ALU with Reservation Stations

[Aleksandar Kostovic]

I see. You split up the stages into the classes. I will start to do it now.

On Wed, Mar 13, 2019 at 5:27 PM Luke Kenneth Casson Leighton <lkcl at lkcl.net>
wrote:

> On Wed, Mar 13, 2019 at 3:58 PM Aleksandar Kostovic <
> alexandar.kostovic at gmail.com> wrote:
>
> > Hey everyone, i am finally back and ready to do this. So Luke, can you
> give
> > me a super fast TL;DL of things that are done(i tried my best to stay up
> to
> > date, but a quick overview would be very much appreciated!) and how
> could i
> > help?
> >
>
>  hi, welcome back, ok i have a video i just uploaded which i've not put a
> description on or anything yet https://youtu.be/iAemcWPgM0Y it's a
> walkthrough of the InputGroup class and the ExamplePipeline class, feel
> free to ignore it entirely or skim it :)
>
>  the next infrastructure stage is to convert InputGroup to conform to the
> Buffered Pipeline stb/busy signal scheme, on both the input _and_ output
> sides.  as InputGroup takes an *array* of stb bits, it's not quite as
> immediately obvious as it seems.
>
> what you could do, aleksander, is start adapting the multiply stages to
> conform to the patterns i created in the add.py code.  i'd suggest starting
> with the multiply_0 stage, taking a copy of the FPAddStage0Mod and
> FPAddStage0 classes and adapting them.
>
> after that, the next stage to try would be to copy FPAddStage1Mod and adapt
> it to create a multiply stage 1 class, however it would *only* have the
> "Else" block (inaccurately commented "# tot[27] zero case", it should be
> tot[-1] case), and note carefully that the sticky bit is set from the
> *bank* of bits from 0..mw instead of just taking the LSB of the mantissa in
> the adder code.
>
> most of what's in add.py will need to move to separate files (probably
> fpbase.py for now) so that they can be shared between mul and add, i
> haven't done that yet as i am still experimenting.
>
> ok must must rest, 00:30 here...
>
> until tomorrow.
>
> l.
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