[libre-riscv-dev] buffered pipeline

[Luke Kenneth Casson Leighton]

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On Wed, Mar 13, 2019 at 8:14 AM Jacob Lifshay <programmerjake at gmail.com>
wrote:

> On Wed, Mar 13, 2019, 00:49 Luke Kenneth Casson Leighton <lkcl at lkcl.net>
> wrote:
>
> > so that's no longer about stopping two sets of logic() block from being
> > created, it's about ensuring that the processing does not occur
> > unnecessarily (i.e. only when input is valid).
> >
> > what do you think?
> >
> In CMOS combinatorial logic, ignoring leakage, it uses power only when the
> logic levels change, so I'd have the registers on the input of the
> combinatorial logic keep the state from the previous clock cycle instead of
> going to 0.
>
>
good point.