[libre-riscv-dev] buffered pipeline

[Jacob Lifshay]

On Wed, Mar 13, 2019, 00:49 Luke Kenneth Casson Leighton <lkcl at lkcl.net>
wrote:

> On Wed, Mar 13, 2019 at 4:21 AM Luke Kenneth Casson Leighton <
> lkcl at lkcl.net>
> wrote:
>
> yes we don't care what the output is: i can see that o_n_stb has gone LOW,
> > so the output 0x21 is known to be invalid: i'd just prefer that the
> output
> > not be computed at all if the input's not valid, to save power.
> >
> > would it be as simple as setting the combinatorial result computation on
> > the condition that i_p_stb is HIGH?
> >
> >
>          # store result of processing in combinatorial temporary
>         result = Signal(16)
>         with m.If(self.i_p_stb): # input is valid: process it
>             m.d.comb += result.eq(self.process(self.i_data))
>         with m.If(o_p_busyn): # not stalled
>             m.d.sync += self.r_data.eq(result)
>
> seems to do the trick: the output is now "0x0000" when o_n_stb goes LOW.
>
> so, dan, in... verilog it would be....
>
> if (i_stb) then
>    result = logic(i_data);
> end;
>
> then replacing all occurrences of "logic(i_data)" with "result", including
> here:
>
> always @(posedge i_clk)
> if (!o_busy)
> r_data <= logic(i_data);
>
> would now be:
>
> always @(posedge i_clk)
> if (!o_busy)
> r_data <= result;
>
> so that's no longer about stopping two sets of logic() block from being
> created, it's about ensuring that the processing does not occur
> unnecessarily (i.e. only when input is valid).
>
> what do you think?
>
In CMOS combinatorial logic, ignoring leakage, it uses power only when the
logic levels change, so I'd have the registers on the input of the
combinatorial logic keep the state from the previous clock cycle instead of
going to 0.

>
> l.
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