[libre-riscv-dev] CAM multiple match policy

[Luke Kenneth Casson Leighton]

[editing and repairing the damaged thread context]

On Tue, Mar 5, 2019 at 8:43 AM Daniel Benusovich
<flyingmonkeys1996 at gmail.com> wrote:
> On some previous date, i wrote:
> >  hurrah! :)  then that would be a usage bug.  as in, if a L1 or L2 or
> > TLB has multiple matching entries, that's a really, really serious and
> > critical fault that would require the processor to halt with extreme
> > prejudice.
> >
> > Sounds good. I implemented the first part of the CAM following the
> interface and have updated the tests for the most part.

 super.

> Its a bit late now though so more tomorrow.

 no problem.

> > like a nmigen PriorityEncoder
> Exactly what I was planning on using haha.

 :)

> > please, do leave it to me to deal with the Trademark issues....
> >
>  Understood. With Xilinx or going to the hw-dev mailing list?

 neither.  with the RISC-V Foundation.

> As for the yosys I need to install it tomorrow and run the sucker so that
> will be fun.

 it also helps ensure that really glaring design errors are avoided,
such as this spectacular fail:

https://git.libre-riscv.org/?p=crowdsupply.git;a=blob;f=images/align_single_fail.png;h=e4004eb02eb89448b9744d9cbdd29e546efc2813;hb=f151751f09347364d91e22c563820f2cfa84f507


> The Make file will be broken for a bit as the interface is
> implemented today and tomorrow.
>
> Two read ports would be cool but I have a feeling it would be a very hungry
> hippo.

 and likely isn't needed.

l.